Sub-System UVM Environment Template

Description

This template is tailored specifically for sub-systems within an ASIC or FPGA with CPU/MPU access and is meant to pair with tb_ss. Simply pick your Clocking, Reset and RAL (Register Abstraction Layer) Agent types and names.

Built-in Virtual Sequences:

Name	Purpose
${clk_agent_name}	Starts Clock generation
${reset_agent_name}	Resets DUT
reg_hw_reset	Runs UVM’s hw_reset sequence either in single block or multiple block (parallel) mode.
reg_bit_bash	Runs UVM’s bit_bash sequence either in single block or multiple block (parallel) mode.

Output

uvme_${name}/
  bin/
    package.py 
  docs/
    env_block_diagram.svg 
  examples/
    instantiation.sv 
    virtual_sequence.sv 
  src/
    comps/
      uvme_${name}_cov_model.sv 
      uvme_${name}_env.sv 
      uvme_${name}_prd.sv 
      uvme_${name}_sb.sv 
      uvme_${name}_vsqr.sv
    obj/
      uvme_${name}_cfg.sv 
      uvme_${name}_cntxt.sv 
    reg/
      uvme_${name}_reg_block.sv 
    seq/
      uvme_${name}_base_vseq.sv 
      uvme_${name}_${clk_agent_name}_vseq.sv 
      uvme_${name}_reg_base_vseq.sv 
      uvme_${name}_reg_base_vseq_ignore_list.sv 
      uvme_${name}_reg_bit_bash_vseq.sv 
      uvme_${name}_reg_bit_bash_vseq_ignore_list.sv 
      uvme_${name}_reg_hw_reset_vseq.sv 
      uvme_${name}_reg_hw_reset_vseq_ignore_list.sv 
      uvme_${name}_${reset_agent_name}_vseq.sv 
      uvme_${name}_vseq_lib.sv 
    uvme_${name}_chkr.sv 
    uvme_${name}_constants.sv 
    uvme_${name}_macros.sv 
    uvme_${name}_pkg.flist 
    uvme_${name}_pkg.flist.xsim 
    uvme_${name}_pkg.sv 
    uvme_${name}_tdefs.sv 
  .gitignore 
  LICENSE.md 
  README.md