Sub-System UVM Test Bench Template

Description

This template is tailored specifically for sub-systems within an ASIC or FPGA with CPU/MPU access and is meant to pair with en_ss. Simply pick your Clocking, Reset and RAL (Register Abstraction Layer) Agent types and names.

Built-in Tests:

Name	Purpose
reg_hw_reset	Runs UVM’s hw_reset sequence either in single block or multiple block (parallel) mode.
reg_bit_bash	Runs UVM’s bit_bash sequence either in single block or multiple block (parallel) mode.

Output

uvmt_${name}/
  bin/
    package.py 
  docs/
    tb_block_diagram.svg 
  examples/
    test.sv 
  src/
    tb/
      uvmt_${name}_probe_if.sv 
      uvmt_${name}_dut_chkr.sv 
      uvmt_${name}_dut_wrap.sv 
      uvmt_${name}_tb.sv 
    tests/
      uvmt_${name}_reg_base_test.sv 
      uvmt_${name}_reg_bit_bash_test.sv 
      uvmt_${name}_reg_hw_reset_test.sv 
      uvmt_${name}_base_test_workarounds.sv 
      uvmt_${name}_base_test.sv 
      uvmt_${name}_test_cfg.sv 
    uvmt_${name}_constants.sv 
    uvmt_${name}_macros.sv 
    uvmt_${name}_pkg.flist 
    uvmt_${name}_pkg.flist.xsim 
    uvmt_${name}_pkg.sv 
    uvmt_${name}_tdefs.sv 
  .gitignore 
  LICENSE.md 
  README.md